K60P100M100SF2RM Datasheet, PDF (244/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Module Signal Description Tables
Chip signal name
MII0_RXCLK
Module signal name
MII_RXCLK
MII0_RXDV
MII_RXDV
MII0_RXD[3:0]
MII0_RXER
MII0_TXCLK
MII0_TXD[3:0]
MII0_TXEN
MII_RXD[3:0]
MII_RXER
MII_TXCLK
MII_TXD[3:0]
MII_TXEN
MII0_TXER
MII_TXER
Description
I/O
In MII mode, provides a
I
timing reference for RXDV,
RXD[3:0], and RXER.
Asserting this input indicates I
the PHY has valid nibbles
present on the MII. RXDV
must remain asserted from
the first recovered nibble of
the frame through to the last
nibble. Asserting RXDV must
start no later than the SFD
and exclude any EOF.
In RMII mode, this pin also
generates the CRS signal.
Contains the Ethernet input I
data transferred from the
PHY to the media-access
controller when RXDV is
asserted.
When asserted with RXDV, I
indicates the PHY detects an
error in the current frame.
Input clock which provides a I
timing reference for TXEN,
TXD[3:0], and TXER.
The serial output Ethernet
O
data and only valid during the
assertion of TXEN.
Indicates when valid nibbles O
are present on the MII. This
signal is asserted with the
first nibble of a preamble and
is negated before the first
TXCLK following the final
nibble of the frame.
When asserted for one or
O
more clock cycles while
TXEN is also asserted, PHY
sends one or more illegal
symbols.
Ethernet RMII Signal Descriptions
Chip signal name
RMII0_MDC
Module signal name
RMII_MDC
Description
I/O
Output clock provides a
O
timing reference to the PHY
for data transfers on the
MDIO signal.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
244
Freescale Semiconductor, Inc.