K60P100M100SF2RM Datasheet, PDF (178/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Private Peripheral Bus (PPB) memory map
4.6 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 4-4. PPB memory map
System 32-bit Address Range
0xE000_0000–0xE000_0FFF
0xE000_1000–0xE000_1FFF
0xE000_2000–0xE000_2FFF
0xE000_3000–0xE000_DFFF
0xE000_E000–0xE000_EFFF
0xE000_F000–0xE003_FFFF
0xE004_0000–0xE004_0FFF
0xE004_1000–0xE004_1FFF
0xE004_2000–0xE004_2FFF
0xE004_3000–0xE004_3FFF
0xE004_4000–0xE007_FFFF
0xE008_0000–0xE008_0FFF
0xE008_1000–0xE008_1FFF
0xE008_2000–0xE00F_EFFF
0xE00F_F000–0xE00F_FFFF
Resource
Instrumentation Trace Macrocell (ITM)
Data Watchpoint and Trace (DWT)
Flash Patch and Breakpoint (FPB)
Reserved
System Control Space (SCS) (for NVIC)
Reserved
Trace Port Interface Unit (TPIU)
Embedded Trace Macrocell (ETM)
Embedded Trace Buffer (ETB)
Embedded Trace Funnel
Reserved
Miscellaneous Control Module (MCM)(including ETB Almost Full)
Memory Mapped Cryptographic Acceleration Unit (MMCAU)
Reserved
ROM Table - allows auto-detection of debug components
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
178
Freescale Semiconductor, Inc.