K60P100M100SF2RM Datasheet, PDF (488/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
• All source reads and destination writes must be configured to the natural boundary of
the programmed transfer size respectively.
• In fixed arbitration mode, a configuration error is caused by any two channel
priorities being equal. All channel priority levels must be unique when fixed
arbitration mode is enabled.
• If a scatter/gather operation is enabled upon channel completion, a configuration
error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-
byte boundary.
• If minor loop channel linking is enabled upon channel completion, a configuration
error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does
not equal the TCDn_BITER[E_LINK] bit.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop
link errors, report as the channel activates and asserts an error interrupt request. A scatter/
gather configuration error is reported when the scatter/gather operation begins at major
loop completion when properly enabled. A minor loop channel link configuration error is
reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and
the appropriate bus error flag set. In this case, the state of the channel's transfer control
descriptor is updated by the eDMA engine with the current source address, destination
address, and current iteration count at the point of the fault. When a system-bus error
occurs, the channel terminates after the read or write transaction, which is already
pipelined after errant access, has completed. If a bus error occurs on the last read prior to
beginning the write sequence, the write executes using the data captured during the bus
error. If a bus error occurs on the last write prior to switching to the next read sequence,
the read sequence executes before the channel terminates due to the destination bus error.
A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer
request is recognized, the DMA engine stops processing the channel. The current read-
write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of
a major or minor loop, the cancel request is discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the ES register is updated
with the cancelled channel number and ECX is set. The TCD of a cancelled channel
contains the source and destination addresses of the last transfer saved in the TCD. If the
channel needs to be restarted, you must re-initialize the TCD because the aforementioned
fields no longer represent the original parameters. When a transfer is cancelled by the
error cancel transfer mechanism, the channel number is loaded into DMA_ES[ERRCHN]
and ECX and VLD are set. In addition, an error interrupt may be generated if enabled.
The occurrence of any error causes the eDMA engine to stop the active channel
immediately, and the appropriate channel bit in the eDMA error register is asserted. At
the same time, the details of the error condition are loaded into the ES register. The major
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
488
Freescale Semiconductor, Inc.