K60P100M100SF2RM Datasheet, PDF (1125/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 43 Real Time Clock (RTC)
43.3.7 Access control
The read access and write access registers are implemented in the chip power domain and
reset on the chip reset (they are not affected by the VBAT POR or the software reset).
They are used to block read or write accesses to each register until the next chip system
reset. When accesses are blocked the bus access is not seen in the VBAT power supply
and does not generate a bus error.
43.3.8 Interrupt
The RTC Interrupt is asserted whenever a status flag and the corresponding interrupt
enable bit are both set. It is always asserted on VBAT POR, software reset and when the
VBAT power supply is powered down. The RTC interrupt is enabled at the chip level by
enabling the chip-specific RTC clock gate control bit. The RTC Interrupt can be used to
wakeup the chip from any low power mode.
The optional RTC seconds interrupt is an edge-sensitive interrupt with a dedicated
interrupt vector that is generated once a second and requires no software overhead (there
is no corresponding status flag to clear). It is enabled in the RTC by the time seconds
interrupt enable bit and enabled at the chip level by setting the chip-specific RTC clock
gate control bit. The RTC seconds interrupt does not cause the RTC wakeup pin to assert.
This interrupt is optional and may not be implemented on all devices.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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