K60P100M100SF2RM Datasheet, PDF (96/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

System modules
Wait
Stop
Power Down
Table 3-28. EWM low-power modes
Module mode
Chip mode
Wait, VLPW
Stop, VLPS, LLS
VLLS3, VLLS2, VLLS1
3.3.11.3 EWM_OUT pin state in low power modes
During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance
state. A user has the option to control the logic state of the pin using an external pull
device or by configuring the internal pull device. When the CPU enters a Run mode from
Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop
mode. When the CPU enters Run mode from Power Down, the pin returns to its reset
state.
3.3.12 Watchdog Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge 0
Register
access
WDOG
Figure 3-16. Watchdog configuration
Table 3-29. Reference links to related information
Topic
Full description
System memory map
Clocking
Power management
Related module
Watchdog
Mode Controller (MC)
Reference
Watchdog
System memory map
Clock distribution
Power management
Mode Controller
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
96
Freescale Semiconductor, Inc.