K60P100M100SF2RM Datasheet, PDF (1620/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
52.5 Functional description
The following sections provide a brief functional description of the major system blocks,
including the data buffer, DMA crossbar switch interface, dual-port memory wrapper,
data/command controller, clock & reset manager and clock generator.
52.5.1 Data buffer
The SDHC uses one configurable data buffer, so that data can be transferred between the
system bus and the SD card, with an optimized manner to maximize throughput between
the two clock domains (that is, the IP peripheral clock, and the master clock). The
following diagram illustrates the buffer scheme. The buffer is used as temporary storage
for data being transferred between the host system and the card. The watermark levels for
read and write are both configurable, and can be any number from 1 to 128 words. The
burst lengths for read and write are also configurable, and can be any number from 1 to
31 words.
Register
Bus
I/F
SDHC Registers
Buffer Control
Status
Sync
Tx / Rx
FIFO
SD Bus
I/F
AHB
Bus
Internal
DMA
Buffer
RAM
Wrapper
Sync
FIFOs
Figure 52-27. SDHC buffer scheme
There are 3 transfer modes to access the data buffer:
• CPU polling mode:
• For a host read operation, when the number of words received in the buffer
meets or exceeds the RDWML watermark value, then by polling the
IRQSTAT[BRR] bit the host driver can read the DATPORT register to fetch the
amount of words set in the WML register from the buffer. The write operation is
similar.
1620
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.