K60P100M100SF2RM Datasheet, PDF (607/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 27 Flash Memory Controller (FMC)
27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)
The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered
0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes
the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 2.
Addresses: FMC_TAGVDW2S0 is 4001_F000h base + 140h offset = 4001_F140h
FMC_TAGVDW2S1 is 4001_F000h base + 144h offset = 4001_F144h
FMC_TAGVDW2S2 is 4001_F000h base + 148h offset = 4001_F148h
FMC_TAGVDW2S3 is 4001_F000h base + 14Ch offset = 4001_F14Ch
FMC_TAGVDW2S4 is 4001_F000h base + 150h offset = 4001_F150h
FMC_TAGVDW2S5 is 4001_F000h base + 154h offset = 4001_F154h
FMC_TAGVDW2S6 is 4001_F000h base + 158h offset = 4001_F158h
FMC_TAGVDW2S7 is 4001_F000h base + 15Ch offset = 4001_F15Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
0
tag[18:6]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_TAGVDW2Sn field descriptions
Field
31–19
Reserved
18–6
tag[18:6]
5–1
Reserved
0
valid
Description
This read-only field is reserved and always has the value zero.
13-bit tag for cache entry
This read-only field is reserved and always has the value zero.
1-bit valid for cache entry
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
607