K60P100M100SF2RM Datasheet, PDF (603/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 27 Flash Memory Controller (FMC)
27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)
This register has a format similar to that for PFB0CR, except it controls the operation of
flash bank 1, and the "global" cache control fields are empty.
Address: FMC_PFB1CR is 4001_F000h base + 8h offset = 4001_F008h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
B1RWSC[3:0]
0
B1MW[1:0]
0
W
Reset 0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
FMC_PFB1CR field descriptions
Field
31–28
B1RWSC[3:0]
27–19
Reserved
18–17
B1MW[1:0]
Bank 1 Read Wait State Control
Description
This read-only field defines the number of wait states required to access the bank 1 flash memory.
The relationship between the read access time of the flash array (expressed in system clock cycles) and
RWSC is defined as:
Access time of flash array [system clocks] = RWSC + 1
The FMC automatically calculates this value based on the ratio of the system clock speed to the flash
clock speed. For example, when this ratio is 4:1, the field's value is 3h.
This read-only field is reserved and always has the value zero.
Bank 1 Memory Width
This read-only field defines the width of the bank 1 memory.
16
Reserved
15–8
Reserved
7–5
Reserved
00 32 bits
01 64 bits
10 Reserved
11 Reserved
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
603