K60P100M100SF2RM Datasheet, PDF (39/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
43.3.4 Time alarm...................................................................................................................................................1124
43.3.5 Update mode................................................................................................................................................1124
43.3.6 Register lock................................................................................................................................................1124
43.3.7 Access control..............................................................................................................................................1125
43.3.8 Interrupt........................................................................................................................................................1125
Chapter 44
10/100-Mbps Ethernet MAC (ENET)
44.1 Introduction...................................................................................................................................................................1127
44.1.1 Overview......................................................................................................................................................1127
44.1.2 Features........................................................................................................................................................1128
44.1.3 Block Diagram.............................................................................................................................................1130
44.2 External Signal Description..........................................................................................................................................1131
44.3 Memory Map/Register Definition.................................................................................................................................1133
44.3.1 Interrupt Event Register (ENET_EIR).........................................................................................................1136
44.3.2 Interrupt Mask Register (ENET_EIMR)......................................................................................................1138
44.3.3 Receive Descriptor Active Register (ENET_RDAR)..................................................................................1141
44.3.4 Transmit Descriptor Active Register (ENET_TDAR).................................................................................1142
44.3.5 Ethernet Control Register (ENET_ECR).....................................................................................................1143
44.3.6 MII Management Frame Register (ENET_MMFR)....................................................................................1144
44.3.7 MII Speed Control Register (ENET_MSCR)..............................................................................................1145
44.3.8 MIB Control Register (ENET_MIBC)........................................................................................................1147
44.3.9 Receive Control Register (ENET_RCR).....................................................................................................1148
44.3.10 Transmit Control Register (ENET_TCR)....................................................................................................1150
44.3.11 Physical Address Lower Register (ENET_PALR)......................................................................................1152
44.3.12 Physical Address Upper Register (ENET_PAUR)......................................................................................1152
44.3.13 Opcode/Pause Duration Register (ENET_OPD).........................................................................................1153
44.3.14 Descriptor Individual Upper Address Register (ENET_IAUR)..................................................................1153
44.3.15 Descriptor Individual Lower Address Register (ENET_IALR)..................................................................1154
44.3.16 Descriptor Group Upper Address Register (ENET_GAUR).......................................................................1154
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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