K60P100M100SF2RM Datasheet, PDF (1144/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
ENET_ECR field descriptions (continued)
Field
3
SLEEP
2
MAGICEN
Description
0 Legacy FEC buffer descriptors and functions enabled.
1 Enhanced frame time-stamping functions enabled.
Sleep mode enable
0 Normal operating mode.
1 Sleep mode.
Magic packet detection enable
Enables/disables magic packet detection.
NOTE: MAGICEN is relevant only if the SLEEP bit is set. If MAGICEN is set, changing the SLEEP bit
enables/disables sleep mode and magic packet detection.
1
ETHEREN
0 Magic detection logic disabled
1 The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
Ethernet enable
Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer descriptors for an aborted
transmit frame are not updated. The uDMA, buffer descriptor, and FIFO control logic are reset, including
the buffer descriptor and FIFO pointers.
Hardware clears this bit under the following conditions:
• RESET is set by software
• An error condition causes the EBERR bit to set.
0
RESET
0 Reception immediately stops and transmission stops after a bad CRC is appended to any currently
transmitted frame.
1 MAC is enabled, and reception and transmission are possible.
Ethernet MAC reset
When this bit is set, it clears the ETHER_EN bit.
44.3.6 MII Management Frame Register (ENET_MMFR)
Performing a write to MMFR triggers a management frame transaction to the PHY
device unless MSCR is programmed to zero.
If MSCR is changed from zero to non-zero during a write to MMFR, an MII frame is
generated with the data previously written to the MMFR. This allows MMFR and MSCR
to be programmed in either order if MSCR is currently zero.
If the MMFR register is written while frame generation is in progress, the frame contents
are altered. Software must use the EIR[MII] interrupt indication to avoid writing to the
MMFR register while frame generation is in progress.
1144
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.