K60P100M100SF2RM Datasheet, PDF (901/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 37 Voltage Reference (VREFV1)
37.2.2 VREF Status and Control Register (VREF_SC)
This register contains the control bits used to enable the internal voltage reference and to
select the VREF mode to be used.
Address: VREF_SC is 4007_4000h base + 1h offset = 4007_4001h
Bit
7
6
5
4
Read
0
VREFEN REGEN Reserved
Write
Reset
0
0
0
0
3
2
1
0
0
VREFST
MODE_LV
0
0
0
0
VREF_SC field descriptions
Field
7
VREFEN
Internal Voltage Reference enable
Description
This bit is used to enable the bandgap reference within the Voltage Reference module.
NOTE: After the VREF is enabled, turning off the clock to the VREF module via the corresponding clock
gate register will not disable the VREF. VREF must be disabled via this VREFEN bit.
6
REGEN
0 The module is disabled.
1 The module is enabled.
Regulator enable
This bit is used to enable the internal 1.75 V VREF regulator to produce a constant internal voltage supply
in order to reduce the sensitivity to external supply noise and variation. The VREF regulator must not be
enabled when entering VLPR, VLPW or VLPS modes.
5
Reserved
4
Reserved
3
Reserved
2
VREFST
0 Internal 1.75 V regulator is disabled.
1 Internal 1.75 V regulator is enabled.
This field is reserved.
This bit must always be written to zero.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Internal Voltage Reference has settled
This bit indicates that the bandgap reference within the Voltage Reference module has completed its
startup and stabilization.
1–0
MODE_LV
0 The bandgap is disabled or not ready.
1 The bandgap is ready.
Buffer Mode selection
These bits select the buffer modes for the Voltage Reference module.
00 Bandgap on only, for stabilization and startup
01 Reserved
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
901