K60P100M100SF2RM Datasheet, PDF (1500/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and registers
UARTx_C3 field descriptions (continued)
Field
0
PEIE
Parity Error Interrupt Enable
Description
This bit enables the parity error flag (S1[PF]) to generate interrupt requests.
0 PF interrupt requests are disabled.
1 PF interrupt requests are enabled.
51.3.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only
receive data register and writes go to the write-only transmit data register.
NOTE
In 8-bit or 9-bit data format, only UART data register (D) needs
to be accessed in order to clear the S1[RDRF] bit (assuming
receiver buffer level is less than RWFIFO[RXWATER]). The
C3 register only needs to be read (prior to the D register) if the
ninth bit of data needs to be captured. Likewise the ED register
only needs to be read (prior to the D register) if the additional
flag data for the dataword needs to be captured.
NOTE
In the normal 8-bit mode (M bit cleared) if the parity is enabled,
you get seven data bits and one parity bit. That one parity bit
will be loaded into the D register. So if you care about only the
data bits, you have to mask off the parity bit from the value you
read out of this register.
NOTE
When transmitting in 9-bit data format and using 8-bit write
instructions, write first to transmit bit 8 in UART control
register 3 (C3[T8]), then D. A write to C3[T8] stores the data in
a temporary register. If D register is written first then the new
data on data bus is stored in D register, while the temporary
value (written by last write to C3[T8]) gets stored in C3[T8]
register.
1500
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.