K60P100M100SF2RM Datasheet, PDF (845/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Note
Chapter 34 Analog-to-Digital Converter (ADC)
Hexadecimal values are designated by a preceding 0x, binary
values designated by a preceding %, and decimal values have
no preceding character.
34.5.1 ADC module initialization example
This section provides details about the ADC module initialization.
34.5.1.1 Initialization sequence
Before the ADC module can be used to complete conversions, an initialization procedure
must be performed. A typical sequence is as follows:
1. Calibrate the ADC by following the calibration instructions in Calibration function.
2. Update the configuration register (CFG) to select the input clock source and the
divide ratio used to generate the internal clock, ADCK. This register is also used for
selecting sample time and low-power configuration.
3. Update status and control register 2 (SC2) to select the conversion trigger (hardware
or software) and compare function options, if enabled.
4. Update status and control register 3 (SC3) to select whether conversions will be
continuous or completed only once (ADCO) and to select whether to perform
hardware averaging.
5. Update the status and control register (SC1:SC1n) to select whether conversions will
be single-ended or differential and to enable or disable conversion complete
interrupts. Also, select the input channel on which to perform conversions.
6. Update PGA register (PGA) to enable or disable PGA and configure appropriate
gain. This register is also used for selecting power mode and whether the module is
chopper stabilized.
34.5.1.2 Pseudo-code example
In this example, the ADC module is set up with interrupts enabled to perform a single 10-
bit conversion at low power with a long sample time on input channel 1, where the
internal ADCK clock is derived from the bus clock divided by 1.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
845