K60P100M100SF2RM Datasheet, PDF (1280/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
Absolute
address
(hex)
USBDCD memory map (continued)
Register name
Width
(in bits)
Access
Reset value
4003_5008 Status Register (USBDCD_STATUS)
32
R
0000_0000h
4003_5010 TIMER0 Register (USBDCD_TIMER0)
32
R/W 0010_0000h
4003_5014 USBDCD_TIMER1
32
R/W 000A_0028h
4003_5018 USBDCD_TIMER2
32
R/W 0028_0001h
Section/
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46.4.3/
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46.4.4/
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46.4.5/
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46.4.6/
1285
46.4.1 Control Register (USBDCD_CONTROL)
Contains the control and interrupt bit fields.
Address: USBDCD_CONTROL is 4003_5000h base + 0h offset = 4003_5000h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
0
0
SR
0
IE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IF
0
0
Reserved
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
USBDCD_CONTROL field descriptions
Field
31–26
Reserved
25
SR
Description
This read-only field is reserved and always has the value zero.
Software Reset
Determines whether a software reset is performed.
24
START
0 Do not perform a software reset.
1 Perform a software reset.
Start Change Detection Sequence
Table continues on the next page...
1280
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.