K60P100M100SF2RM Datasheet, PDF (1419/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 49 SPI (DSPI)
49.4.2 Serial Peripheral Interface (SPI) Configuration
The SPI Configuration transfers data serially using a shift register and a selection of
programmable transfer attributes. The DSPI is in SPI Configuration when the DCONF
field in the MCR is 0b00. The SPI frames can be 32 bits long. The host CPU or a DMA
controller transfers the SPI data from the external to DSPI RAM queues to a transmit
FIFO (TX FIFO) buffer. The received data is stored in entries in the Receive FIFO (RX
FIFO) buffer. The host CPU or the DMA controller transfers the received data from the
RX FIFO to memory external to the DSPI. The FIFO buffers operation is described in
Transmit First In First Out (TX FIFO) Buffering Mechanism, and Receive First In First
Out (RX FIFO) Buffering Mechanism. The interrupt and DMA request conditions are
described in Interrupts/DMA Requests.
The SPI Configuration supports two block-specific modes —master mode and slave
mode. The FIFO operations are similar for both modes. The main difference is that in
master mode the DSPI initiates and controls the transfer according to the fields in the SPI
command field of the TX FIFO entry. In slave mode, the DSPI only responds to transfers
initiated by a bus master external to the DSPI and the SPI command field space is used
for 16 most significant bit of the transmit data.
49.4.2.1 Master Mode
In SPI master mode the DSPI initiates the serial transfers by controlling the Serial
Communications Clock (SCK) and the Peripheral Chip Select (PCS) signals. The SPI
command field in the executing TX FIFO entry determines which CTAR registers will be
used to set the transfer attributes and which PCS signals to assert. The command field
also contains various bits that help with queue management and transfer protocol. See
DSPI PUSH TX FIFO Register (PUSHR) for details on the SPI command fields. The
data field in the executing TX FIFO entry is loaded into the shift register and shifted out
on the Serial Out (SOUT) pin. In SPI master mode, each SPI frame to be transmitted has
a command associated with it allowing for transfer attribute control on a frame by frame
basis.
49.4.2.2 Slave Mode
In SPI slave mode the DSPI responds to transfers initiated by a SPI bus master. The DSPI
does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase
and frame size must be set for successful communication with a SPI master. The SPI
slave mode transfer attributes are set in the CTAR0. The data is shifted out with MSB
first. Shifting out of LSB is not supported in this mode.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1419