K60P100M100SF2RM Datasheet, PDF (1082/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
41.4.3.4 Glitch filter bypassed
In pulse counter mode when the glitch filter is bypassed, the selected input source
increments the LPTMR counter register every time it asserts. Before the LPTMR is first
enabled, the selected input source is forced to asserted. This is to prevent the LPTMR
counter register from incrementing if the selected input source is already asserted when
the LPTMR is first enabled.
41.4.4 LPTMR compare
When the LPTMR counter register equals the value of the LPTMR compare register and
increments, the following events occur:
• Timer compare flag is set
• LPTMR interrupt is generated if Timer Interrupt Enable is also set
• LPTMR hardware trigger is generated
• LPTMR counter register is reset if the free running counter bit is clear
When the LPTMR is enabled, the LPTMR compare register can only be altered when the
timer compare flag is set. When updating the LPTMR compare register, the LPTMR
compare register must be written and the timer compare flag must be cleared before the
LPTMR counter has incremented past the new LPTMR compare value.
41.4.5 LPTMR counter
The LPTMR counter register increments by one on every:
• prescaler clock (time counter mode with prescaler bypassed)
• prescaler output (time counter mode with prescaler enabled)
• input source assertion (pulse counter mode with glitch filter bypassed)
• glitch filter output (pulse counter mode with glitch filter enabled).
The LPTMR counter register is reset when the LPTMR is disabled or if the counter
register overflows. If the CSR[TFC] control bit is set then the LPTMR counter register is
also reset whenever the CSR[TCF] status flag is set.
The LPTMR counter register continues incrementing when the core is halted in debug
mode.
1082
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.