K60P100M100SF2RM Datasheet, PDF (1682/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

I2S signal descriptions
Continuous
STCK, SRCK
STFS, SRFS
Early
STFS, SRFS
Gated STCK
STXD
SRXD
76 5 4 3 2 1 0
8-bit Data
76 5 4 3 2 1 0
76
76
Bit-length frame sync
Word-length frame sync
Figure 53-3. Serial clock and frame sync timing
The following table shows a list of clock pin configurations.
Table 53-3. Clock pin configurations
CR
RCR
TCR
[SYN] RXDIR RFDIR TXDIR TFDIR
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1
1
0
1
SRCK
STCK
Asynchronous Mode
RCK in
TCK in
RCK in
TCK in
RCK in
TCK in
RCK in
TCK in
RCK in
TCK out
RCK in
TCK out
RCK in
TCK out
RCK in
TCK out
RCK out
TCK in
RCK out
TCK in
RCK out
TCK in
RCK out
TCK in
SRFS
RFS in
RFS in
RFS out
RFS out
RFS in
RFS in
RFS out
RFS out
RFS in
RFS in
RFS out
RFS out
Table continues on the next page...
STFS
TFS in
TFS out
TFS in
TFS out
TFS in
TFS out
TFS in
TFS out
TFS in
TFS out
TFS in
TFS out
1682
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.