K60P100M100SF2RM Datasheet, PDF (1171/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
5–2
TMODE
1
Reserved
0
TDRE
Chapter 44 10/100-Mbps Ethernet MAC (ENET)
ENET_TCSRn field descriptions (continued)
Timer Mode
Description
Updating the Timer Mode field takes a few cycles to register since it is synchronized to the 1588 clock.
The version of Timer Mode returned on a read is from the 1588 clock domain. When changing Timer
Mode always disable the channel and read this register to verify the channel is disabled first.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1010
10x1
1100
1110
1111
Timer Channel is disabled.
Timer Channel is configured for Input Capture on rising edge
Timer Channel is configured for Input Capture on falling edge
Timer Channel is configured for Input Capture on both edges
Timer Channel is configured for Output Compare - software only
Timer Channel is configured for Output Compare - toggle output on compare
Timer Channel is configured for Output Compare - clear output on compare
Timer Channel is configured for Output Compare - set output on compare
Reserved
Timer Channel is configured for Output Compare - clear output on compare, set output on
overflow
Timer Channel is configured for Output Compare - set output on compare, clear output on
overflow
Reserved
Timer Channel is configured for Output Compare - pulse output low on compare for one 1588
clock cycle
Timer Channel is configured for Output Compare - pulse output high on compare for one 1588
clock cycle
This read-only field is reserved and always has the value zero.
Timer DMA Request Enable
0 DMA request is disabled
1 DMA request is enabled
44.3.42 Timer Compare Capture Register (ENET_TCCRn)
Addresses: ENET_TCCR0 is 400C_0000h base + 60Ch offset = 400C_060Ch
ENET_TCCR1 is 400C_0000h base + 614h offset = 400C_0614h
ENET_TCCR2 is 400C_0000h base + 61Ch offset = 400C_061Ch
ENET_TCCR3 is 400C_0000h base + 624h offset = 400C_0624h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TCC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1171