K60P100M100SF2RM Datasheet, PDF (1205/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 44 10/100-Mbps Ethernet MAC (ENET)
• The GRA interrupt is asserted, when transitioned into stopped
• In hardware freeze mode, the GRA interrupt does not wait for the application write
completion and asserts when the transmit state machine (line side of TX FIFO)
reaches its stopped state.
44.4.9.4.2 Graceful Receive Stop (GRS)
When gracefully stopped, the MAC is no longer writing frames into the receive FIFO.
The receive datapath stops after any ongoing frame reception has been completed
normally, if any of the following conditions occur:
• MAC is placed in sleep mode (by software or the processor is in stop mode). The
MAC continues to receive frames and hunt for magic packets if enabled (see Magic
Packet Detection). However, no frames are written into the receive FIFO, and
therefore are not forwarded to the application.
• The MAC is in hardware freeze mode. The MAC does not accept any frames from
the MII.
When the receive datapath is stopped the following events occur:
• If the RX is in the stopped state, RCR[GRS] is set
• The GRA interrupt is asserted when the transmitter and receiver are stopped
• Any ongoing receive transaction to the application (RX FIFO read) continues
normally until the frame is completed (end of packet (eop)). After this, the following
occurs:
• When sleep mode is active, all further frames are discarded, flushing the RX
FIFO
• In hardware freeze mode, no further frames are delivered to the application and
they stay in the receive FIFO.
Note
The assertion of GRS does not wait for an ongoing transaction
on the application side of the FIFO (FIFO read).
44.4.9.4.3 Graceful Stop Interrupt (GRA)
The graceful stopped interrupt (GRA) is asserted for the following conditions:
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1205