K60P100M100SF2RM Datasheet, PDF (1361/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 48 CAN (FlexCAN)
3. Read the contents of the Mailbox. Once Mailbox is locked now, its contents won’t be
modified by FlexCAN Move-in processes. See Section "Move-in".
4. Acknowledge the proper flag at IFLAG registers.
5. Read the Free Running Timer. It is optional but recommended to unlock Mailbox as
soon as possible and make it available for reception.
The CPU should synchronize to frame reception by the status flag bit for the specific
Mailbox in one of the IFLAG Registers and not by the CODE field of that Mailbox.
Polling the CODE field does not work because once a frame was received and the CPU
services the Mailbox (by reading the C/S word followed by unlocking the Mailbox), the
CODE field will not return to EMPTY. It will remain FULL, as explained in Table
48-109 . If the CPU tries to workaround this behavior by writing to the C/S word to force
an EMPTY code after reading the Mailbox without a prior safe inactivation, a newly
received frame matching the filter of that Mailbox may be lost.
CAUTION
In summary: never do polling by reading directly the C/S word
of the Mailboxes. Instead, read the IFLAG registers.
Note that the received frame’s Identifier field is always stored in the matching Mailbox,
thus the contents of the ID field in an Mailbox may change if the match was due to
masking. Note also that FlexCAN does receive frames transmitted by itself if there exists
a matching Rx Mailbox, provided the MCR[SRXDIS] bit is not asserted. If the
MCR[SRXDIS] bit is asserted, FlexCAN will not store frames transmitted by itself in any
MB, even if it contains a matching MB, and no interrupt flag or interrupt signal will be
generated due to the frame reception.
To be able to receive CAN frames through the Rx FIFO, the CPU must enable and
configure the Rx FIFOduring Freeze Mode (see Rx FIFO). Upon receiving the Frames
Available in Rx FIFO interrupt (see the description of the IFLAG[BUF5I] "Frames
available in Rx FIFO" bit in the IMASK1 register), the CPU should service the received
frame using the following procedure:
1. Read the Control and Status word (optional – needed only if a mask was used for
IDE and RTR bits)
2. Read the ID field (optional – needed only if a mask was used)
3. Read the Data field
4. Read the RXFIR register (optional)
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1361