K60P100M100SF2RM Datasheet, PDF (1705/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 53 Integrated interchip sound (I2S)
53.3.11 I²S Receive Clock Control Registers (I2Sx_RCCR)
The I2S Transmit and Receive Control (TCCR and RCCR) registers are 19-bit, read/write
control registers used to direct the operation of the I2S. The Clock and Reset Module
(CRM) can source the I2S clock (network clock) from multiple sources and perform
fractional division to support commonly used audio bit rates. The CRM can maintain the
network clock frequency at a constant rate even in cases where the peripheral clock
frequency changes. These registers control the I2S clock generator, bit and frame sync
rates, word length, and number of words per frame for the serial data. The TCCR register
is dedicated to the transmit section, and the RCCR register is dedicated to the receive
section except in Synchronous mode, in which the TCCR register controls both the
receive and transmit sections. Power-on reset clears all TCCR and RCCR bits. I2S reset
does not affect the TCCR and RCCR bits. The control bits are described in the following
paragraphs. Although the bit patterns of the TCCR and RCCR registers are the same, the
contents of these two registers can be programmed differently.
Addresses: I2S0_RCCR is 4002_F000h base + 28h offset = 4002_F028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
WL
DC
PM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCCR field descriptions
Field
31–19
Reserved
18
DIV2
Description
This read-only field is reserved and always has the value zero.
Divide By 2.
This bit controls a divide-by-two divider in series with the rest of the prescalers.
17
PSR
0 Divider bypassed.
1 Divider used to divide clock by 2.
Prescaler Range.
This bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. It extends the range
of the prescaler for those cases where a slower bit clock is required.
16–13
WL
0 Prescaler bypassed.
1 Prescaler used to divide clock by 8.
Word Length Control.
These bits are used to control the length of the data words being transferred by the I²S. These bits control
the Word Length Divider in the Clock Generator. They also control the frame sync pulse length when the
FSL bit is cleared. In I2S Master mode, the I²S works with a fixed word length of 32, and the WL bits are
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1705