K60P100M100SF2RM Datasheet, PDF (1600/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_IRQSTAT field descriptions (continued)
Field
3
DINT
0b Not ready to write buffer
1b Ready to write buffer
DMA Interrupt
Description
Occurs only when the internal DMA finishes the data transfer successfully. Whenever errors occur during
data transfer, this bit will not be set. Instead, the DMAE bit will be set. Either Simple DMA or ADMA
finishes data transferring, this bit will be set.
2
BGE
0b No DMA Interrupt
1b DMA Interrupt is generated
Block Gap Event
If the PROCTL[SABGREQ] is set, this bit is set when a read or write transaction is stopped at a block gap.
If PROCTL[SABGREQ] is not set to 1, this bit is not set to 1.
In the case of a read transaction: This bit is set at the falling edge of the DAT line active status (When the
transaction is stopped at SD Bus timing). The read wait must be supported in order to use this function.
In the case of write transaction: This bit is set at the falling edge of write transfer active status (After
getting CRC status at SD bus timing).
0b No block gap event
1b Transaction stopped at block gap
1
Transfer Complete
TC
This bit is set when a read or write transfer is completed.
In the case of a read transaction: This bit is set at the falling edge of the read transfer active status. There
are two cases in which this interrupt is generated. The first is when a data transfer is completed as
specified by the data length (after the last data has been read to the host system). The second is when
data has stopped at the block gap and completed the data transfer by setting the PROCTL[SABGREQ]
(after valid data has been read to the host system).
In the case of a write transaction: This bit is set at the falling edge of the DAT line active status. There are
two cases in which this interrupt is generated. The first is when the last data is written to the SD card as
specified by the data length and the busy signal is released. The second is when data transfers are
stopped at the block gap, by setting the PROCTL[SABGREQ], and the data transfers are completed.
(after valid data is written to the SD card and the busy signal released).
0b Transfer not complete
1b Transfer complete
0
Command Complete
CC
This bit is set when you receive the end bit of the command response (except Auto CMD12). Refer to the
PRSSTAT[CIHB].
0b Command not complete
1b Command complete
1600
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.