K60P100M100SF2RM Datasheet, PDF (78/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Core modules
• NVICIABR2
• NVICIPR21
• To determine the particular IRQ's bitfield location within these particular registers:
• NVICISER2, NVICICER2, NVICISPR2, NVICICPR2, NVICIABR2 bit
location = IRQ mod 32 = 21
• NVICIPR21 bitfield starting location = 8 * (IRQ mod 4) + 4 = 12
Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR21
bitfield range is 12-15
Therefore, the following bitfield locations are used to configure the LPTMR interrupts:
• NVICISER2[21]
• NVICICER2[21]
• NVICISPR2[21]
• NVICICPR2[21]
• NVICIABR2[21]
• NVICIPR21[15:12]
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC)
Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at http://
www.arm.com.
Clock logic
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Wake-up
requests
Module
Module
Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration
Topic
System memory map
Clocking
Table 3-6. Reference links to related information
Related module
Reference
System memory map
Clock distribution
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
78
Freescale Semiconductor, Inc.