K60P100M100SF2RM Datasheet, PDF (165/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 4
Memory Map
4.1 Introduction
This device contains various memories and memory-mapped peripherals which are
located in one 32-bit contiguous memory space. This chapter describes the memory and
peripheral locations within that memory space.
4.2 System memory map
The following table shows the high-level device memory map.
Table 4-1. System memory map
System 32-bit Address Range
0x0000_0000–0x0FFF_FFFF
0x1000_0000–0x13FF_FFFF
0x1400_0000–0x17FF_FFFF
0x1800_0000–0x1FFF_FFFF
0x2000_0000–0x200F_FFFF
0x2010_0000–0x21FF_FFFF
0x2200_0000–0x23FF_FFFF
Destination Slave
Program flash and read-only data
(Includes exception vectors in first 1024 bytes)
• For MK60DN256ZVLL10: Reserved
• For MK60DX256ZVLL10: FlexNVM
• For MK60DN512ZVLL10: Reserved
For devices with FlexNVM: FlexRAM
For devices with program flash only: Programming
acceleration RAM
SRAM_L: Lower SRAM (ICODE/DCODE)
SRAM_U: Upper SRAM bitband region
Reserved
Aliased to SRAM_U bitband
0x2400_0000–0x3FFF_FFFF
0x4000_0000–0x4007_FFFF
Reserved
Bitband region for peripheral bridge 0 (AIPS-Lite0)
Table continues on the next page...
Access
All masters
All masters
All masters
All masters
All masters
–
Cortex-M4 core
only
–
Cortex-M4 core &
DMA/EzPort
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
165