K60P100M100SF2RM Datasheet, PDF (1581/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
52.4.6 Command Response 1 (SDHC_CMDRSP1)
This register is used to store part 1 of the response bits from the card.
Address: SDHC_CMDRSP1 is 400B_1000h base + 14h offset = 400B_1014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMDRSP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_CMDRSP1 field descriptions
Field
31–0
CMDRSP1
Command Response 1
Description
52.4.7 Command Response 2 (SDHC_CMDRSP2)
This register is used to store part 2 of the response bits from the card.
Address: SDHC_CMDRSP2 is 400B_1000h base + 18h offset = 400B_1018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CMDRSP2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_CMDRSP2 field descriptions
Field
31–0
CMDRSP2
Command Response 2
Description
52.4.8 Command Response 3 (SDHC_CMDRSP3)
This register is used to store part 3 of the response bits from the card.
The following table describes the mapping of command responses from the SD bus to
command response registers for each response type. In the table, R[ ] refers to a bit range
within the response data as transmitted on the SD bus.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1581