K60P100M100SF2RM Datasheet, PDF (1340/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
CANx_CTRL2 field descriptions (continued)
Field
Description
If TASD is 0 then the arbitration start is not delayed, thus the CPU has less time to configure a Tx MB for
the next arbitration, but more time is reserved for arbitration. In the other hand, if TASD is 24 then the
CPU can configure a Tx MB later and less time is reserved for arbitration.
If too little time is reserved for arbitration the FlexCAN may be not able to find winner MBs in time to
compete with other nodes for the CAN bus. If the arbitration ends too much time before the first bit of
Intermission field then there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
not the best to be transmitted.
The optimal configuration for TASD can be calculated as:
18
MRP
17
RRS
16
EACEN
TASD = 25 - {f_CANCLK x [MAXB + 3 - (RFEN x 8) - (RFEN x RFFN x 2)] x 2} /
{f_SYS x [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] x (PRESDIV+1)}
where:
• f_CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in Hz;
• f_SYS is the peripheral clock, in Hz;
• MAXMB is the value in CTRL1[MAXMB] field;
• RFEN is the value in CTRL1[RFEN] bit;
• RFFN is the value in CTRL2[RFFN] field;
• PSEG1 is the value in CTRL1[PSEG1] field;
• PSEG2 is the value in CTRL1[PSEG2] field;
• PROPSEG is the value in CTRL1[PROPSEG] field;
• PRESDIV is the value in CTRL1[PRESDIV] field.
See Section "Arbitration process" and Section "Protocol Timing" for more details.
NOTE: The recommended value for TASD is 22.
Mailboxes Reception Priority
If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching
continues on the Rx FIFO. This bit can only be written in Freeze mode as it is blocked by hardware in
other modes.
0 Matching starts from Rx FIFO and continues on Mailboxes.
1 Matching starts from Mailboxes and continues on Rx FIFO.
Remote Request Storing
If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the
corresponding Message Buffer in the same fashion of a Data Frame. No automatic Remote Response
Frame will be generated.
If this bit is negated the Remote Request Frame is submitted to a matching process and an automatic
Remote Response Frame is generated if a Message Buffer with CODE=0b1010 is found with the same
ID.
This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
0 Remote Response Frame is generated.
1 Remote Request Frame is stored.
Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes
This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes filters with their corresponding
bits in the incoming frame by the matching process. This bit does not affect matching for Rx FIFO. This bit
can only be written in Freeze mode as it is blocked by hardware in other modes.
Table continues on the next page...
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.