K60P100M100SF2RM Datasheet, PDF (521/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 23 Watchdog Timer (WDOG)
non-time-out exception (see Generated Resets and Interrupts). You need to unlock the
watchdog before enabling it. A system reset brings the watchdog out of the disabled
mode.
23.3.6 Low Power Modes of Operation
• In Wait mode, if the WDOG is enabled (WAIT_EN = 1), it can run on bus clock or
low power oscillator clock (CLK_SRC = x) to generate interrupt (IRQ_RST_EN=1)
followed by a reset on time-out. After reset the WDOG reset counter increments by
one.
• In Stop mode where the bus clock is gated, the WDOG can run only on low power
oscillator clock (CLK_SRC=0) if it is enabled in stop (STOP_EN=1). In this case,
the WDOG runs to time-out twice, and then generates a reset from its backup
circuitry. Therefore, if you program the watchdog to time-out after 100 ms and then
enter such a stop mode, the reset will occur after 200 ms. Also, in this case no
interrupt will be generated irrespective of the value of IRQ_RST_EN bit. After
WDOG reset, the WDOG reset counter will also not increment.
• In Power-down mode, the watchdog is powered off.
23.3.7 Debug Modes of Operation
You can program the watchdog to disable in debug modes (through DBG_EN bit in the
watchdog control register). This results in the watchdog timer pausing for the duration of
the mode. Register read/writes are still allowed, which means that operations like:
refresh, unlock etc. are allowed. On exit from the mode, the timer resumes its operation
from the point of pausing.
The entry of the system into the debug mode does not excuse it from compulsorily
configuring the watchdog in the WCT time after unlock (unless the system bus clock is
gated off, in which case the internal state machine pauses too). Failing to do so still
results in a reset (or interrupt-then-reset, if enabled) to the system. Also, all the exception
conditions that result in a reset to the system (see Generated Resets and Interrupts) are
still valid in this mode. So, if an exception condition occurs and the system bus clock is
on, a reset occurs (or interrupt-then-reset, if enabled).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
521