K60P100M100SF2RM Datasheet, PDF (891/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
3
LPEN
2
DACBWIEN
1
DACBTIEN
0
DACBBIEN
Chapter 36 12-bit Digital-to-Analog Converter (DAC)
DACx_C0 field descriptions (continued)
DAC low power control
Description
Refer to the device data sheet's 12-bit DAC electrical characteristics for details on the impact of the
modes below.
0 high power mode.
1 low power mode.
DAC buffer watermark interrupt enable
0 The DAC buffer watermark interrupt is disabled.
1 The DAC buffer watermark interrupt is enabled.
DAC buffer read pointer top flag interrupt enable
0 The DAC buffer read pointer top flag interrupt is disabled.
1 The DAC buffer read pointer top flag interrupt is enabled.
DAC buffer read pointer bottom flag interrupt enable
0 The DAC buffer read pointer bottom flag interrupt is disabled.
1 The DAC buffer read pointer bottom flag interrupt is enabled.
36.4.5 DAC Control Register 1 (DACx_C1)
Addresses: DAC0_C1 is 400C_C000h base + 22h offset = 400C_C022h
Bit
Read
Write
Reset
7
DMAEN
0
6
5
0
0
0
4
3
DACBFWM
0
0
2
1
DACBFMD
0
0
0
DACBFEN
0
DACx_C1 field descriptions
Field
7
DMAEN
6–5
Reserved
4–3
DACBFWM
DMA enable select
Description
0 DMA disabled.
1 DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And
interrupts will not be presented on this module at the same time.
This read-only field is reserved and always has the value zero.
DAC buffer watermark select
This bitfield controls when the DAC buffer watermark flag will be set. When the DAC buffer read pointer
reaches the word defined by this bitfield, from 1 to 4 words away from the upper limit (DACBUP), the DAC
buffer watermark flag will be set. This allows user configuration of the watermark interrupt.
00 1 word
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
891