K60P100M100SF2RM Datasheet, PDF (973/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 39 FlexTimer (FTM)
39.3.21 Quadrature Decoder Control and Status (FTMx_QDCTRL)
This register has the control and status bits for the quadrature decoder mode.
Addresses: FTM0_QDCTRL is 4003_8000h base + 80h offset = 4003_8080h
FTM1_QDCTRL is 4003_9000h base + 80h offset = 4003_9080h
FTM2_QDCTRL is 400B_8000h base + 80h offset = 400B_8080h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FTMx_QDCTRL field descriptions
Field
31–8
Reserved
7
PHAFLTREN
Description
This read-only field is reserved and always has the value zero.
Phase A Input Filter Enable
Enables the filter for the quadrature decoder phase A input. The filter value for the phase A input is
defined by the CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero.
6
PHBFLTREN
0 Phase A input filter is disabled.
1 Phase A input filter is enabled.
Phase B Input Filter Enable
Enables the filter for the quadrature decoder phase B input. The filter value for the phase B input is
defined by the CH1FVAL field of FILTER. The phase B filter is also disabled when CH1FVAL is zero.
5
PHAPOL
0 Phase B input filter is disabled.
1 Phase B input filter is enabled.
Phase A Input Polarity
Selects the polarity for the quadrature decoder phase A input.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
973