K60P100M100SF2RM Datasheet, PDF (601/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 27 Flash Memory Controller (FMC)
FMC_PFB0CR field descriptions (continued)
Field
Description
27–24
Cache Lock Way x
CLCK_WAY[3:0]
These bits determine if the given cache way is locked such that its contents will not be displaced by future
misses.
The bit setting definitions are for each bit in the field.
0 Cache way is unlocked and may be displaced
1 Cache way is locked and its contents are not displaced
23–20
CINV_WAY[3:0]
Cache Invalidate Way x
These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is
written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents
are cleared. This field always reads as zero.
Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System
software is required to maintain memory coherency when any segment of the flash memory is
programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event
is completed and before the new memory image is accessed.
The bit setting definitions are for each bit in the field.
19
S_B_INV
0 No cache way invalidation for the corresponding cache
1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
Invalidate Prefetch Speculation Buffer
This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be
invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are
immediately cleared. This bit always reads as zero.
18–17
B0MW[1:0]
0 Speculation buffer and single entry buffer are not affected.
1 Invalidate (clear) speculation buffer and single entry buffer.
Bank 0 Memory Width
This read-only field defines the width of the bank 0 memory.
16
Reserved
15–8
Reserved
7–5
CRC[2:0]
00 32 bits
01 64 bits
1x Reserved
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Cache Replacement Control
This 3-bit field defines the replacement algorithm for accesses that are cached.
000 LRU replacement algorithm per set across all four ways
001 Reserved
010 Independent LRU with ways [0-1] for ifetches, [2-3] for data
011 Independent LRU with ways [0-2] for ifetches, [3] for data
1xx Reserved
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
601