K60P100M100SF2RM Datasheet, PDF (836/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
34.4.5.6 Conversion time examples
The following examples use Figure 34-95 and the information provided in Table 34-107
through Table 34-111.
34.4.5.6.1 Typical conversion time configuration
A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected
as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency
of 8 MHz, long sample time disabled and high speed conversion disabled. The
conversion time for a single conversion is calculated by using Figure 34-95 and the
information provided in Table 34-107 through Table 34-111. The table below list the
variables of Figure 34-95.
Table 34-112. Typical conversion time
Variable
SFCAdder
AverageNum
BCT
LSTAdder
HSCAdder
Time
5 ADCK cycles + 5 bus clock cycles
1
20 ADCK cycles
0
0
The resulting conversion time is generated using the parameters listed in the proceeding
table. Therefore, for a bus clock equal to 8 MHz and an ADCK equal to 8 MHz the
resulting conversion time is 3.75 µs.
34.4.5.6.2 Long conversion time configuration
A configuration for long ADC conversion is: 16-bit differential mode with the bus clock
selected as the input clock source, the input clock divide-by-8 ratio selected, a bus
frequency of 8 MHz, long sample time enabled, configured for longest adder, high speed
conversion disabled, and average enabled for 32 conversions. The conversion time for
this conversion is calculated by using Figure 34-95 and the information provided in Table
34-107 through Table 34-111. The following table lists the variables of the Figure 34-95.
Variable
SFCAdder
AverageNum
BCT
LSTAdder
Table 34-113. Typical conversion time
Time
3 ADCK cycles + 5 bus clock cycles
32
34 ADCK cycles
20 ADCK cycles
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
836
Freescale Semiconductor, Inc.