K60P100M100SF2RM Datasheet, PDF (834/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
ADC Configuration
1
11
1
Sample time (ADCK cycles)
8
The total conversion time depends upon: the sample time (as determined by ADLSMP
and ADLSTS bits), the MCU bus frequency, the conversion mode (as determined by
MODE and SC1n[DIFF] bits), the high speed configuration (ADHSC bit), and the
frequency of the conversion clock (f_ADCK).
The ADHSC bit is used to configure a higher clock input frequency. This will allow
faster overall conversion times. To meet internal ADC timing requirements, the ADHSC
bit adds additional ADCK cycles. Conversions with ADHSC = 1 take two more ADCK
cycles. ADHSC should be used when the ADCLK exceeds the limit for ADHSC = 0.
After the module becomes active, sampling of the input begins. ADLSMP and ADLSTS
select between sample times based on the conversion mode that is selected. When
sampling is completed, the converter is isolated from the input channel and a successive
approximation algorithm is performed to determine the digital value of the analog signal.
The result of the conversion is transferred to Rn upon completion of the conversion
algorithm.
If the bus frequency is less than the f_ADCK frequency, precise sample time for continuous
conversions cannot be guaranteed when short sample is enabled (ADLSMP=0).
The maximum total conversion time is determined by the clock source chosen and the
divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide
ratio is specified by the ADIV bits.
The maximum total conversion time for all configurations is summarized in the equation
below. Refer to the following tables for the variables referenced in the equation.
Figure 34-95. Conversion time equation
Table 34-107. Single or first continuous time adder (SFCAdder)
ADLSMP
1
1
1
0
0
0
ADACKE
N
x
1
0
x
1
0
ADICLK
0x, 10
11
11
0x, 10
11
11
Single or first continuous time adder (SFCAdder)
3 ADCK cycles + 5 bus clock cycles
3 ADCK cycles + 5 bus clock cycles¹
5 μs + 3 ADCK cycles + 5 bus clock cycles
5 ADCK cycles + 5 bus clock cycles
5 ADCK cycles + 5 bus clock cycles¹
5 μs + 5 ADCK cycles + 5 bus clock cycles
1. To achieve this time, ADACKEN must be 1 for at least 5 μs prior to the conversion is initiated.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
834
Freescale Semiconductor, Inc.