K60P100M100SF2RM Datasheet, PDF (435/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 21 Direct Memory Access Controller (eDMA)
DMA memory map (continued)
Absolute
address
(hex)
Register name
4000_801E Clear Error Register (DMA_CERR)
4000_801F Clear Interrupt Request Register (DMA_CINT)
4000_8024 Interrupt Request Register (DMA_INT)
4000_802C Error Register (DMA_ERR)
4000_8034 Hardware Request Status Register (DMA_HRS)
4000_8100 Channel n Priority Register (DMA_DCHPRI3)
4000_8101 Channel n Priority Register (DMA_DCHPRI2)
4000_8102 Channel n Priority Register (DMA_DCHPRI1)
4000_8103 Channel n Priority Register (DMA_DCHPRI0)
4000_8104 Channel n Priority Register (DMA_DCHPRI7)
4000_8105 Channel n Priority Register (DMA_DCHPRI6)
4000_8106 Channel n Priority Register (DMA_DCHPRI5)
4000_8107 Channel n Priority Register (DMA_DCHPRI4)
4000_8108 Channel n Priority Register (DMA_DCHPRI11)
4000_8109 Channel n Priority Register (DMA_DCHPRI10)
4000_810A Channel n Priority Register (DMA_DCHPRI9)
4000_810B Channel n Priority Register (DMA_DCHPRI8)
4000_810C Channel n Priority Register (DMA_DCHPRI15)
4000_810D Channel n Priority Register (DMA_DCHPRI14)
Width
(in bits)
Access
Reset value
Section/
page
W
8
(always
reads
00h
zero)
21.3.11/
462
W
8
(always
reads
00h
zero)
21.3.12/
463
32
R/W
0000_0000h
21.3.13/
463
32
R/W
0000_0000h
21.3.14/
466
32
R/W
0000_0000h
21.3.15/
468
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
8
R/W
Undefined
21.3.16/
470
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
435