K60P100M100SF2RM Datasheet, PDF (731/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 29 External Bus Interface (FlexBus)
Table 29-30. Transfer Size and Port Size Translation
Port Size PS[1:0]
01 (8-bit)
1x (16-bit)
00 (32-bit)
Transfer Size FB_TSIZ[1:0]
10 (16-bits)
00 (32-bits)
11 (16 bytes)
00 (32 bits)
11 (16 bytes)
11 (line)
Burst-Inhibited: Number of Transfers
Burst Enabled: Number of Beats
2
4
16
2
8
4
The FlexBus can support 2-1-1-1 burst cycles to maximize system performance. Delaying
termination of the cycle can add wait states. If internal termination is used, different wait
state counters can be used for the first access and the following beats.
The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be
declared burst-inhibited for reads and writes by clearing the appropriate
CSCRn[BSTR,BSTW] bits.
The following figure shows a 32-bit read to an 8-bit device programmed for burst enable.
The transfer results in a 4-beat burst and the data is driven on FB_AD[31:24]. The
transfer size is driven at 32-bit (00) throughout the bus cycle.
Note
In non-multiplexed address/data mode, the address on FB_A
increments only during internally-terminated burst cycles. The
first address is driven throughout the entire burst for externally-
terminated cycles.
In multiplexed address/data mode, the address is driven on
FB_AD only during the first cycle for all terminated cycles.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
731