K60P100M100SF2RM Datasheet, PDF (1013/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

begin
Chapter 39 FlexTimer (FTM)
legacy
PWM synchronization
SYNCMODE
bit ?
=1
enhanced PWM synchronization
MOD register is
updated by software trigger
SWWRBUF ^{= 0}
bit ?
=1
end
software
trigger
SWSYNC
bit ?
=1
FTM counter is reset by
software trigger
SWRSTCNT ^{= 1}
bit ?
wait the next selected
loading point
update MOD with
its buffer value
update MOD with
its buffer value
MOD register is
updated by hardware trigger
HWWRBUF ^{= 0}
bit ?
=1
end
hardware
trigger
0 = TRIGn
bit ?
=1
wait hardware trigger n
HWTRIGMODE ^{= 1}
bit ?
=0
clear TRIGn bit
clear SWSYNC bit
end
clear SWSYNC bit
end
FTM counter is reset by
hardware trigger
0 = _HWRSTCNT = 1
bit ?
wait the next selected
loading point
update MOD with
its buffer value
update MOD with
its buffer value
end
end
Figure 39-208. MOD Register Synchronization Flowchart
In the case of legacy PWM synchronization, the MOD register synchronization depends
on PWMSYNC and REINIT bits according to the following description.
If (SYNCMODE = 0), (PWMSYNC = 0) and (REINIT = 0) then this synchronization is
made on the next selected loading point after an enabled trigger event takes place. If the
trigger event was a software trigger then the SWSYNC bit is cleared on the next selected
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1013