K60P100M100SF2RM Datasheet, PDF (1626/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
Because the DMA burst length can't change during a data transfer for an external DMA
transfer, the watermark level (read or write) must be a divisor of the block size. If it is
not, transferring of the block may cause buffer under-run (read operation) or over-run
(write operation). For example, if the block size is 512 bytes, the watermark level of read
(or write) must be a power of two between 1 and 128. For processor core polling access,
as the last access in the block transfer can be controlled by software, there is no such
issue. The watermark level can be any value, even larger than the block size (but no
greater than 128 words). This is because the actual number of bytes transferred by the
software can be controlled and does not exceed the block size in each transfer.
The SDHC also supports non-word aligned block size, as long as the card supports that
block size. In this case, the watermark level should be set as the number of words. For
example, if the block size is 31 bytes, the watermark level can be set to any number of
word. For this case, the BLKATTR[BLKSIZE] bits shall be set as 1fh. For the CPU
polling access, the burst length can be 1 to 128 words, without restriction. This is because
the software will transfer 8 words, and the SDHC will also set the IRQSTAT[BWR] or
IRQSTAT[BRR] bits when the remaining data does not violate data buffer. Refer to
DMA burst length for more details about the dynamic watermark level of the data buffer.
For the above example, even though 8 words are transferred via the DATPORT register,
the SDHC will transfer only 31 bytes over the SD bus, as required by the
BLKATTR[BLKSIZE] bits. In this data transfer, with non-word aligned block size, the
endian mode should be set cautiously, or invalid data will be transferred to/from the card.
52.5.2 DMA crossbar switch interface
The internal DMA implements a DMA engine and the crossbar switch master. When the
internal DMA is enabled (XFERTYP[DMAEN] is set), the interrupt status bits are set if
they are enabled. To avoid setting them, clear IRQSTATEN[BWRSEN, BRRSEN]. The
following diagram illustrates the DMA crossbar switch interface block.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.