K60P100M100SF2RM Datasheet, PDF (788/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
RNG_CMD field descriptions (continued)
Field
Description
• When RNG_SR[BUSY] is cleared, or
• If set simultaneously with GS, self test takes precedence and is completed first.
When self test completes, this bit automatically clears and an interrupt may be generated if all requested
operations are complete.
0 Not in self test mode.
1 Self test mode.
33.3.3 RNGB Control Register (RNG_CR)
Through use of this register, the RNGB can be programmed to provide slightly different
functionality based on its desired use.
Address: RNG_CR is 400A_0000h base + 8h offset = 400A_0008h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
0
0
AR
FUFMOD
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RNG_CR field descriptions
Field
31–10
Reserved
9–7
Reserved
6
MASKERR
Description
This read-only field is reserved and always has the value zero.
Reserved, must be cleared.
This read-only field is reserved and always has the value zero.
Reserved, must be cleared.
Mask error interrupt.
Masks interrupts generated by errors in the RNGB. These errors can still be viewed in RNG_ESR.
NOTE: Since masked errors do not interrupt the operation of the RNGB and thus hide potentially fatal
errors or conditions that could result in corrupted results, it is strongly recommended that errors
only be masked while debugging. All errors are considered fatal, requiring the RNGB to be reset.
Until the a reset occurs, the RNGB does not service any random data.
0 No mask applied.
1 Mask applied to the error interrupt.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
788
Freescale Semiconductor, Inc.