K60P100M100SF2RM Datasheet, PDF (632/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Registers
FTFL_FSTAT field descriptions (continued)
Field
Description
The CCIF bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization
sequence. Depending on how quickly the read occurs after reset release, the user may or may not see
the 0 hardware reset value.
6
RDCOLERR
0 FTFL command or EEPROM file system operation in progress
1 FTFL command or EEPROM file system operation has completed
FTFL Read Collision Error Flag
The RDCOLERR error bit indicates that the MCU attempted a read from an FTFL resource that was being
manipulated by an FTFL command (CCIF=0). Any simultaneous access is detected as a collision error by
the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit is
cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
5
ACCERR
0 No collision error detected
1 Collision error detected
Flash Access Error Flag
The ACCERR error bit indicates an illegal access has occurred to an FTFL resource caused by a violation
of the command write sequence or issuing an illegal FTFL command. While ACCERR is set, the CCIF
flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to
the ACCERR bit has no effect.
4
FPVIOL
0 No access error detected
1 Access error detected
Flash Protection Violation Flag
The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area
of program flash or data flash memory during a command write sequence or a write was attempted to a
protected area of the FlexRAM while enabled for EEPROM . While FPVIOL is set, the CCIF flag cannot
be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL
bit has no effect.
3–1
Reserved
0
MGSTAT0
0 No protection violation detected
1 Protection violation detected
This read-only field is reserved and always has the value zero.
Memory Controller Command Completion Status Flag
The MGSTAT0 status flag is set if an error is detected during execution of an FTFL command or during
the flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the
other error flags in this register.
The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution
when CCIF=1 and before the next command has been launched. At some point during the execution of
"command-N+1," the previous result is discarded and any previous error is cleared.
28.34.2 Flash Configuration Register (FTFL_FCNFG)
This register provides information on the current functional state of the FTFL module.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
632
Freescale Semiconductor, Inc.