K60P100M100SF2RM Datasheet, PDF (1608/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_AC12ERR field descriptions (continued)
Field
7
CNIBAC12E
Description
Command Not Issued By Auto CMD12 Error
Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12 error (D04-D01) in this
register.
6–5
Reserved
4
AC12IE
0b No error
1b Not issued
This read-only field is reserved and always has the value zero.
Auto CMD12 Index Error
Occurs if the command index error occurs in response to a command.
3
AC12CE
0b No error
1b Error, the CMD index in response is not CMD12
Auto CMD12 CRC Error
Occurs when detecting a CRC error in the command response.
2
AC12EBE
0b No CRC error
1b CRC Error met in auto CMD12 Response
Auto CMD12 End Bit Error
Occurs when detecting that the end bit of command response is 0 which should be 1.
1
AC12TOE
0b No error
1b End bit error generated
Auto CMD12 Timeout Error
Occurs if no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is
set to 1, the other error status bits (2-4) have no meaning.
0
AC12NE
0b No error
1b Time out
Auto CMD12 Not Executed
If memory multiple block data transfer is not started, due to a command error, this bit is not set because it
is not necessary to issue an auto CMD12. Setting this bit to 1 means the SDHC cannot issue the auto
CMD12 to stop a memory multiple block data transfer due to some error. If this bit is set to 1, other error
status bits (1-4) have no meaning.
0b Executed
1b Not executed
1608
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.