K60P100M100SF2RM Datasheet, PDF (568/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization / Application Information
24.5.3.2 Example 2: Moving from PEE to BLPI Mode: MCGOUTCLK
Frequency =32 kHz
In this example, the MCG will move through the proper operational modes from PEE
mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see
previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.First, the code
sequence will be described. Then a flowchart will be included which illustrates the
sequence.
1. First, PEE must transition to PBE mode:
a. C1 = 0x90
• C1[CLKS] set to 2'b10 in order to switch the system clock source to the
external reference clock.
b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is
selected to feed MCGOUTCLK.
2. Then, PBE must transition either directly to FBE mode or first through BLPE mode
and then to FBE mode:
a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1
b. BLPE/FBE: C6 = 0x00
• C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value
of 3'b010, the FLL divider is set to 128, resulting in a reference frequency of
4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 3'b010
(necessary to achieve required 31.25-39.06 kHz FLL reference frequency
with an 4 MHz external source frequency), it must be changed prior to
clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the
MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV]
value does not matter.
c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to
FBE mode.
d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the
PLLS clock is the FLL.
3. Next, FBE mode transitions into FBI mode:
a. C1 = 0x54
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
568
Freescale Semiconductor, Inc.