K60P100M100SF2RM Datasheet, PDF (1724/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
next time slot. Failing to reload the TX register before the TXSR is finished shifting
(empty) causes a transmitter underrun and the TUE error bit is set. In case the FIFO is
enabled, the ISR[TFE] flag is set in accordance with the watermark setting and this flag
causes the transmitter interrupt to occur.
Clearing the TE bit disables the transmitter after completion of transmission of the
current frame. Setting the TE bit enables transmission from the next frame. During that
time the STXD port is disabled. The TE bit should be cleared after the ISR[TDE] bit is
set to ensure that all pending data is transmitted.
To summarize, the network mode transmitter generates interrupts every enabled time slot
(when FIFO is disabled) and requires the processor to respond to each enabled time slot.
These responses may be:
• Write data in data register to enable transmission in the next time slot.
• Configure the time slot register to disable transmission in the next time slot (unless
time slot is already masked by TMSK[STMSK] register bit).
• Do nothing—transmit underrun occurs at the beginning of the next time slot and the
previous data is re-transmitted.
In two-channel mode, both channels (data registers, FIFOs, interrupts, and DMA
requests) operate in the same manner, as described above. The only difference is
interrupts related to the second channel are generated only if this mode of operation is
selected (ISR[TDE1] is low by default).
53.4.1.2.2 Network mode receive
The receiver portion of the I²S is enabled when the CR[I2SEN and RE] bits are set.
However, the receive enable only takes place during that time slot if RE is enabled before
the second to last bit of the word. If the RE bit is cleared, the receiver is disabled at the
end of the current frame. The I²S module is capable of finding the start of the next frame
automatically. When the word is completely received, it is transferred to the RX register,
which sets the ISR[RDR] bit. This causes a receive interrupt to occur if the receiver
interrupt is enabled (IER[RIE] is set) and receive data ready is enabled (IER[RDR0EN]
and IER[RDR1EN] is set). The second data word (second time slot in the frame) begins
shifting in immediately after the transfer of the first data word to the RX register. The
processor has to read the data from the receive data register (which clears ISR[RDR])
before the second data word is completely received (ready to transfer to RX data register)
or a receive overrun error occurs (the ISR[ROE] bit is set).
An interrupt can occur after the reception of each enabled data word or the user can poll
the ISR[RDR] flag. The response can be:
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.