K60P100M100SF2RM Datasheet, PDF (1337/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
5
BUF5I
4–0
BUF4TO0I
Chapter 48 CAN (FlexCAN)
CANx_IFLAG1 field descriptions (continued)
Description
0 No occurrence of MB6 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO
almost full (when MCR[RFEN]=1)
1 MB6 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO almost full (when
MCR[RFEN]=1)
Buffer MB5 Interrupt or "Frames available in Rx FIFO"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB5.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF5I flag represents "Frames available in Rx FIFO" when MCR[RFEN] is set. In this case, the flag
indicates that at least one frame is available to be read from the Rx FIFO.
0 No occurrence of MB5 completing transmission/reception (when MCR[RFEN]=0) or of frame(s)
available in the Rx FIFO (when MCR[RFEN]=1)
1 MB5 completed transmission/reception (when MCR[RFEN]=0) or frame(s) available in the Rx FIFO
(when MCR[RFEN]=1)
Buffer MB_i Interrupt or "reserved"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag the interrupts for MB4 to
MB0.
NOTE: These flags are cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU
writes.
The BUF4TO0I flags are reserved when MCR[RFEN] is set.
0 The corresponding buffer has no occurrence of successfully completed transmission or reception
(when MCR[RFEN]=0).
1 The corresponding buffer has successfully completed transmission or reception (when
MCR[RFEN]=0).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1337