K60P100M100SF2RM Datasheet, PDF (1026/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
before the inverting
channel (n+1) output
before the inverting
write 1 to INV(m) bit
INV(m) bit buffer
INVCTRL register
synchronization
INV(m) bit
channel (n) output
after the inverting
channel (n+1) output
after the inverting
NOTE
INV(m) bit selects the inverting to the pair channels (n) and (n+1).
Figure 39-226. Channels (n) and (n+1) Outputs After the Inverting in Low-True
(ELSnB:ELSnA = X:1) Combine Mode
Note
It is expected that the inverting feature be used only in combine
mode.
39.4.13 Software Output Control
The software output control forces the channel output according to software defined
values at a specific time in the PWM generation.
The software output control is selected when (FTMEN = 1), (QUADEN = 0),
(DECAPEN = 0), (COMBINE = 1), (CPWMS = 0), and (CHnOC = 1). The CHnOC bit
enables the software output control for a specific channel output and the CHnOCV
selects the value that is forced to this channel output.
Both CHnOC and CHnOCV bits in SWOCTRL register are buffered and updated with
their buffer value according to SWOCTRL Register Synchronization.
The following figure shows the channels (n) and (n+1) outputs signals when the software
output control is used. In this case the channels (n) and (n+1) are set to combine and
complementary mode.
1026
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.