K60P100M100SF2RM Datasheet, PDF (703/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
25–24
Reserved
23
SWSEN
22
EXTS
21–20
ASET
19–18
RDAH
17–16
WRAH
15–10
WS
Chapter 29 External Bus Interface (FlexBus)
FB_CSCRn field descriptions (continued)
Description
(CSCRn[WS]). If the SWSEN bit is cleared, the WS value is used for all burst transfers and this field is
ignored.
This read-only field is reserved and always has the value zero.
Secondary wait state enable
0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers
1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst
transfer secondary terminations
Extended address latch enable
0 FB_TS/FB_ALE asserts for one bus clock cycle
1 _{FB_TS/FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts}
Address setup
Controls the assertion of the chip-select with respect to assertion of a valid address and attributes. The
address and attributes are considered valid at the same time FB_TS/FB_ALE asserts.
00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
01 Assert FB_CSn on second rising clock edge after address is asserted.
10 Assert FB_CSn on third rising clock edge after address is asserted.
11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
Read address hold or deselect
This field controls the address and attribute hold time after the termination during a read cycle that hits in
the chip-select address space.
NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer
to a port size smaller than the transfer size, the hold time is only added after the last bus cycle.
The number of cycles the address and attributes are held after FB_CSn negation depends on the value of
CSCRn[AA].
00 If AA is cleared, 1 cycle. If AA is set, 0 cycles.
01 If AA is cleared, 2 cycles. If AA is set, 1 cycle.
10 If AA is cleared, 3 cycles. If AA is set, 2 cycles.
11 If AA is cleared, 4 cycles. If AA is set, 3 cycles.
Write address hold or deselect
Write address hold or deselect. This field controls the address, data, and attribute hold time after the
termination of a write cycle that hits in the chip-select address space.
NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer
to a port size smaller than the transfer size, the hold time is only added after the last bus cycle.
00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
01 Hold address and attributes two cycles after FB_CSn negates on writes.
10 Hold address and attributes three cycles after FB_CSn negates on writes.
11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
Wait states
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
703