K60P100M100SF2RM Datasheet, PDF (1722/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
Gated
CLK
TX
DATA
STXD
SRXD
RX
DATA
Figure 53-48. Normal mode timing - external gated clock
53.4.1.2 Network mode
Network mode creates a time division multiplexed (TDM) network, such as a TDM
CODEC network or a network of DSPs. In continuous clock mode, a frame sync occurs
at the beginning of each frame. In this mode, the frame is divided into more than one time
slot. During each time slot, one data word can be transferred. Each time slot is then
assigned to an appropriate codec or DSP on the network. The processor can be a master
device that controls its own private network, or a slave device that is connected to an
existing TDM network and occupies a few time slots.
The frame sync signal indicates the beginning of a new data frame. Each data frame is
divided into time slots and transmission and/or reception of one data word can occur in
each time slot (rather than in just the frame sync time slot as in normal mode).
The frame rate dividers, controlled by the DC bits, select two to thirty-two time slots per
frame. The length of the frame is determined by:
• Period of the serial bit clock (PSR, PM bits for internal clock, or the frequency of the
external clock on the STCK port)
• Number of bits per sample (WL bits)
• Number of time slots per frame (DC bits)
In network mode, data can be transmitted in any time slot. The distinction of the network
mode is that each time slot is identified with respect to the frame sync (data word time).
This time slot identification allows the option of transmitting data during the time slot by
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.