K60P100M100SF2RM Datasheet, PDF (450/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
DMA_CR field descriptions (continued)
Field
0
Reserved
Description
0 When in debug mode, the DMA continues to operate.
1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
This read-only field is reserved and always has the value zero.
21.3.2 Error Status Register (DMA_ES)
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
• A configuration error, that is:
• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle
See the Error Reporting and Handling section for more details.
Address: DMA_ES is 4000_8000h base + 4h offset = 4000_8004h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R VLD
0
ECX
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
R 0 CPE
0
11
10
9
ERRCHN
8
7
6
5
4
3
2
1
0
SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_ES field descriptions
Field
31
VLD
30–17
Reserved
16
ECX
Logical OR of all ERR status bits
Description
0 No ERR bits are set
1 At least one ERR bit is set indicating a valid error exists that has not been cleared
This read-only field is reserved and always has the value zero.
Transfer Cancelled
0 No cancelled transfers
1 The last recorded entry was a cancelled transfer by the error cancel transfer input
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
450
Freescale Semiconductor, Inc.