K60P100M100SF2RM Datasheet, PDF (47/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
49.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn)............................................................................................1416
49.4 Functional Description..................................................................................................................................................1417
49.4.1 Start and Stop of DSPI Transfers.................................................................................................................1418
49.4.2 Serial Peripheral Interface (SPI) Configuration...........................................................................................1418
49.4.3 DSPI Baud Rate and Clock Delay Generation.............................................................................................1422
49.4.4 Transfer Formats..........................................................................................................................................1426
49.4.5 Continuous Serial Communications Clock..................................................................................................1431
49.4.6 Slave Mode Operation Constraints..............................................................................................................1432
49.4.7 Interrupts/DMA Requests............................................................................................................................1433
49.4.8 Power Saving Features.................................................................................................................................1435
49.5 Initialization/Application Information..........................................................................................................................1436
49.5.1 How to Manage DSPI Queues.....................................................................................................................1436
49.5.2 Switching Master and Slave Mode..............................................................................................................1437
49.5.3 Baud Rate Settings.......................................................................................................................................1438
49.5.4 Delay Settings..............................................................................................................................................1438
49.5.5 Calculation of FIFO Pointer Addresses.......................................................................................................1439
Chapter 50
Inter-Integrated Circuit (I2C)
50.1 Introduction...................................................................................................................................................................1443
50.1.1 Features........................................................................................................................................................1443
50.1.2 Modes of Operation.....................................................................................................................................1444
50.1.3 Block Diagram.............................................................................................................................................1444
50.2 I2C Signal Descriptions................................................................................................................................................1445
50.3 Memory Map and Register Descriptions......................................................................................................................1445
50.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................1447
50.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................1447
50.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................1448
50.3.4 I2C Status Register (I2Cx_S).......................................................................................................................1450
50.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................1452
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
47