K60P100M100SF2RM Datasheet, PDF (824/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register Definition
ADCx_PGA field descriptions (continued)
Field
15–0
Reserved
Description
1000
1001
1010
1011
1100
1101
1110
1111
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
This read-only field is reserved and always has the value zero.
34.3.19 ADC minus-side general calibration value register
(ADCx_CLMD)
CLMx contain calibration information that is generated by the calibration function. These
registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are
automatically set once the self calibration sequence is done (CAL is cleared). If these
registers are written by the user after calibration, the linearity error specifications may not
be met.
Addresses: ADC0_CLMD is 4003_B000h base + 54h offset = 4003_B054h
ADC1_CLMD is 400B_B000h base + 54h offset = 400B_B054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
CLMD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
ADCx_CLMD field descriptions
Field
31–6
Reserved
5–0
CLMD
Description
This read-only field is reserved and always has the value zero.
Calibration value
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
824
Freescale Semiconductor, Inc.