K60P100M100SF2RM Datasheet, PDF (1157/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 44 10/100-Mbps Ethernet MAC (ENET)
44.3.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR)
TDSR provides a pointer to the start of the circular transmit buffer descriptor queue in
external memory. This pointer must be 64-bit aligned (bits 2–0 must be zero); however, it
is recommended to be 128-bit aligned (evenly divisible by 16). This register is undefined
at reset and must be initialized prior to operation.
Address: ENET_TDSR is 400C_0000h base + 184h offset = 400C_0184h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
X_DES_START
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENET_TDSR field descriptions
Field
Description
31–3
Pointer to the start of the transmit buffer descriptor queue.
X_DES_START
2–0
Reserved
This read-only field is reserved and always has the value zero.
44.3.21 Maximum Receive Buffer Size Register (ENET_MRBR)
The MRBR is a user-programmable register that dictates the maximum size of all receive
buffers. This value should take into consideration that the receive CRC is always written
into the last receive buffer. To allow one maximum size frame per buffer, MRBR must be
set to RCR[MAX_FL] or larger. To properly align the buffer, MRBR must be evenly
divisible by 16. To ensure this, bits 3–0 are forced low.
To minimize bus utilization (descriptor fetches), set MRBR greater than or equal to 256
bytes. The MRBR register is undefined at reset and must be initialized by the user.
Address: ENET_MRBR is 400C_0000h base + 188h offset = 400C_0188h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
0
R_BUF_SIZE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1157