K60P100M100SF2RM Datasheet, PDF (1586/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_PRSSTAT field descriptions (continued)
Field
Description
During a write transaction, a block gap event interrupt is generated when this bit is changed to 0, as result
of the stop at block gap request being set. This status is useful for the host driver in determining when to
issue commands during write busy state.
7
SDOFF
0b No valid data
1b Transferring data
SD Clock Gated Off Internally
This status bit indicates that the SD clock is internally gated off, because of buffer over/under-run or read
pause without read wait assertion, or the driver has cleared SYSCTL[SDCLKEN] bit to stop the SD clock.
This bit is for the host driver to debug data transaction on the SD bus.
6
PEROFF
0b SD clock is active
1b SD clock is gated off
SDHC clock
Gated Off Internally
This status bit indicates that the SDHC clock is internally gated off. This bit is for the host driver to debug
transaction on the SD bus. When INITA bit is set, SDHC sending 80 clock cycles to the card, the
SDCLKEN bit must be ‘1’ to enable the output card clock, otherwise the
SDHC clock
will never be gate off, so
SDHC clock
and
bus clock
will be always active.
5
HCKOFF
0b SDHC clock
is active
1b _{SDHC clock}
is gated off
System Clock
Gated Off Internally
This status bit indicates that the system clock is internally gated off. This bit is for the host driver to debug
during a data transfer.
4
IPGOFF
0b System clock
is active
1b _{System clock}
is gated off
Bus Clock
Gated Off Internally
This status bit indicates that the bus clock is internally gated off. This bit is for the host driver to debug.
Table continues on the next page...
1586
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.